`timescale 1ns/100ps

module de_to_fsync_tb;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK;
reg nRESET;
reg nRESET_1;
reg fsync_in;
reg enable_fsync;
reg enable_fsync_1;
reg [15:0] h_total;
reg [15:0] v_total;
reg [15:0] h_active;
reg [15:0] h_active_front;
reg [15:0] h_active_front_sync;
reg [15:0] v_active;
reg [15:0] v_active_front;
reg [15:0] v_active_front_sync;

initial
begin
	SYSCLK = 0;
	nRESET = 0;
	nRESET_1 = 0;
	fsync_in = 0;
	enable_fsync = 1;
	enable_fsync_1 = 0;
	h_total = 20-1;
	v_total = 14-1;
	h_active = 12-1;
	h_active_front = 14-1;
	h_active_front_sync = 16-1;
	v_active = 8-1;
	v_active_front = 10-1;
	v_active_front_sync = 12-1;
end


/*iverilog */
initial
begin            
    $dumpfile("de_to_fsync_tb.vcd");        //生成的vcd文件名称
    $dumpvars(0, de_to_fsync_tb);    //tb模块名称
end
/*iverilog */

initial

begin
	#(SYSCLK_PERIOD * 2 )
        nRESET = 1'b1;
	#228
		nRESET_1 = 1'b1;
	#4000
		enable_fsync_1 = 1'b1;	
	#8000
		$finish;
end

always @(SYSCLK)
begin
	#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end

wire data_enable_0;
wire de_fsync_out;

video_timming video_timming_0 (
	// input
	.clk(SYSCLK),
	.rst_n(nRESET),
	.fsync_in(fsync_in),
	.enable_fsync(enable_fsync),
	.h_total(h_total),
	.v_total(v_total),
	.h_active(h_active),
	.h_active_front(h_active_front),
	.h_active_front_sync(h_active_front_sync),
	.v_active(v_active),
	.v_active_front(v_active_front),
	.v_active_front_sync(v_active_front_sync),
	
	// output
	.hsync(hsync_0),
	.vsync(vsync_0),
	.data_enable(data_enable_0),
	.fsync_out(fsync_out_0)	

);

de_to_fsync de_to_fsync_0(
	.clk(SYSCLK),
	.de(data_enable_0),
	.rst_n(nRESET),
	.fsync_out(de_fsync_out)
);

wire data_enable_2;

video_timming video_timming_1 (
	// input
	.clk(SYSCLK),
	.rst_n(nRESET_1),
	.fsync_in(de_fsync_out),
	.enable_fsync(enable_fsync_1),
	.h_total(h_total),
	.v_total(v_total),
	.h_active(h_active),
	.h_active_front(h_active_front),
	.h_active_front_sync(h_active_front_sync),
	.v_active(v_active),
	.v_active_front(v_active_front),
	.v_active_front_sync(v_active_front_sync),
	
	// output
	.hsync(hsync_1),
	.vsync(vsync_1),
	.data_enable(data_enable_1),
	.fsync_out(fsync_out_1)	

);


endmodule